The present invention relates to a receiving circuit, and in particular a single-ended signal to differential signal conversion circuit.
A differential amplifier often provides a differential output voltage in response to two input voltages. FIG. 1 illustrates a circuit 100 that is often referred to as a differential amplifier. A voltage source VDD is applied to sources of transistors 101 and 103. Gates of transistors 101 and 103 are coupled to ground 109. Drains of transistors 101 and 103 are coupled to terminals 121 and 122, respectively. Terminals 121 and 122 output a differential output voltage VOUT. Drains of transistors 101 and 103 are also coupled to drains of transistors 102 and 104, respectively. An input voltage VIN is applied to a gate of transistor 102 and a reference voltage VREF is applied to the gate of transistor 104. Sources of transistors 102 and 104 are coupled to a current source, and in particular transistor 108 having a source coupled to ground 109 and a drain coupled to the sources of transistors 102 and 104. A bias voltage VBIAS is applied to a gate of transistor 108. Transistors 101 and 102 form a first electrical path from a voltage source VDD and current source (transistor) 108 while transistors 103 and 104 form a second electrical path. An advantage of such a differential amplifier is that the matched electrical paths cancel undesirable voltage swings common to input voltages, which may for instance be caused by temperature variations or noise, whereas differences between the input voltages are amplified.
A differential output voltage VOUT, illustrated by curve 203 in FIG. 2c, is output at terminals 121 and 122 in response to voltage VIN illustrated by curve 200 in FIG. 2a. In particular, curve 202, illustrated in FIG. 2b, represents an output voltage at terminal 121 and curve 201 represents an output voltage at terminal 122 in response to VIN represented by curve 200 illustrated in FIG. 2a. Reference voltage VREF is represented by curve (flat line) 204 in FIG. 2a. The two output voltages at terminals 121 and 122 are combined to obtain the differential output voltage VOUT as illustrated by curve 203 in FIG. 2c. Differential output voltage VOUT has a duty cycle of approximately 53.6%, as opposed to an ideal 50%.
A receiving circuit often includes amplifying stage and sampling stage. Differential amplifiers are often used in amplifying stage of a receiving circuit in order to restore/amplify the incoming data. Ideally, the amplifier should maintain the timing information of the incoming data in order to have the sampling stage operate correctly, i.e., if a periodic incoming data has 50% duty cycle, the amplified differential signal should also have 50% duty cycle.
However, certain serial data signals are single-ended signals. This single-ended signal usually needs to be converted into a differential signal, and a differential amplifier is commonly used for this purpose. However, a differential amplifier may create erroneous or unbalanced amplified differential signals and degrade timing margin of a receiving circuit. For example, when a double date rate transmitter is transmitting a single-ended signal of xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d during a clock cycle, an optimal signal sampling stage will receive an amplified signal with an evenly distributed bit duration of xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d. This will typically ensure both xe2x80x9c1xe2x80x9d and xe2x80x9c0xe2x80x9d have optimal timing margin. If any one of these two bits xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d have a longer bit duration than the other, system timing margin is degraded. A data input signal may include either a relatively large and/or small voltage level swing. A differential amplifier may be designed to handle a relatively low voltage level swing. This means a differential amplifier is acting as a gain stage. Yet a gain stage generally does not handle input signals properly with large voltage level swings, as one of the input transistors will be pushed out of saturation. For relatively large single-ended input voltage signals as illustrated in FIG. 2a, where one of the input devices is pushed into linear region, current steering does not work properly. Thus, the characteristic of the amplified differential signals may be different for large voltage swings in large data eyes than for small voltage swings in small data eyes. Furthermore, the input voltage swings of a receiving circuit may not be predictable. Thus, an amplifier that can properly operate with both large and small voltage swing is desirable.
Some differential amplifiers have addressed unbalanced amplified differential signals by providing unbalanced loads on respective electrical paths. This technique may reduce duty cycle error for large input voltage levels, but it degrades performance for small voltage inputs. Further, such a technique does not offer common mode noise rejection, since each electrical path should be ideally symmetrical in nature.
Therefore, it is desirable to provide a circuit and method for providing a balanced differential output voltage signal for both relatively small and large voltage level inputs while also being able to reject noise. It is also desirable to provide an apparatus that produces an improved duty cycle clock signal and thereby reduce data error rates of incoming serial single-ended data.
A circuit, apparatus and method for providing a balanced differential signal from incoming single-ended serial data having high or low voltage swings are provided in embodiments of the present invention.
In an embodiment of the present invention, a circuit comprises a voltage source and a current source coupled to a node. A first electrical path is coupled to the voltage source and the node. A second electrical path is coupled to the voltage source and the node. The first path includes a first transistor having a first gate and a first channel. The first gate is adapted to receive a reference voltage. The second path includes a second transistor having a second gate and a second channel. The second gate is adapted to receive a data voltage that is variable as a positive and negative voltage relative to the reference voltage. A variable resistor is coupled to the first electrical path and the second electrical path, and provides a predetermined resistance responsive to a node voltage at the node.
According to another embodiment of the present invention, the circuit further comprises a signal processing circuit that is coupled to the variable resistor and the node. The signal processing circuit generates a control signal responsive to the node voltage.
According to an embodiment of the present invention, the circuit comprises a third transistor having a third gate and a third channel. The first path includes the third channel having a first resistance between the voltage source and the first transistor. The second path includes a fourth transistor having a fourth gate and a fourth channel having a second resistance between the voltage source and the second transistor.
According to another embodiment of the present invention, the current source includes a fifth transistor having a drain coupled to the node and a source coupled to a ground. The fifth transistor has a gate adapted to receive a bias voltage.
According to still another embodiment of the present invention, the variable resistor includes a sixth transistor having a source, a drain and a gate. The source is coupled to the first path and the drain is coupled to the second path.
According to an embodiment of the present invention, the signal processing circuit comprises a seventh transistor having a source, a drain and a gate. The source is coupled to the voltage source and the gate is coupled to the sixth transistor gate. An eighth transistor has a source, a drain and a gate. The eighth transistor drain is coupled to the seventh transistor drain and the eighth transistor gate is coupled to the node.
According to an embodiment of the present invention, the first transistor, second transistor, fifth transistor, and eighth transistor are n-type transistors.
According to an embodiment of the present invention, the third transistor, fourth transistor, sixth transistor, and seventh transistor are p-type transistors.
According to an embodiment of the present invention, the circuit is a differential amplifier circuit used in a double data rate receiving circuit for amplifying a single-ended data signal and converting the single-ended data signal into a differential signal used by a sampling stage.
According to an embodiment of the present invention, the circuit is in a memory device.
According to an embodiment of the present invention, the circuit is in a memory device controller.
According to an embodiment of the present invention, an apparatus comprising a transmit circuit transmits serial data to a receive circuit that generates an output signal responsive to the serial data. The receive circuit includes a first electrical path coupled to a voltage source and a node. A second electrical path is coupled to the voltage source and the node. A first transistor having a first gate and a first channel is included in the first path. The first transistor gate is adapted to receive a reference voltage. A second transistor having a second gate and a second channel is included in the second path. The second transistor gate is adapted to receive a data voltage, corresponding to the serial data that is variable as a positive and negative voltage relative to the reference voltage. A variable resistor is coupled to the first electrical path and the second electrical path. The variable resistor provides a predetermined resistance responsive to a node voltage at the node.
According to an embodiment of the present invention, a method comprises the steps of receiving serial data having a voltage level and applying the voltage level to a first transistor in a first electrical path. A reference voltage is applied to a second transistor in a second electrical path. The first electronic path is coupled to the second electronic path at a node. A variable resistance is provided between the first electronic path and the second electronic path responsive to a voltage at the node. Output voltage is output from the first and second electrical paths. A voltage source is applied to the first and second electrical paths and a current source is applied to the node. An amplified and converted data signal is generated responsive to the output voltage.
These and other embodiments of the present invention, as well as other aspects and advantages are described in more detail in conjunction with the figures, the detailed description, and the claims that follow.